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general description the mx29f002t/b is a 2-mega bit flash memory organized as 256k bytes of 8 bits only. mxic's flash memories offer the most cost-effective and re- liable read/write non-volatile random access memory. the mx29f002t/b is packaged in 32-pin pdip,plcc and 32-pin tsop (i ). it is designed to be reprogrammed and erased in-system or in-stand- ard eprom programmers. the standard mx29f002t/b offers access time as fast as 70ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx29f002t/b has separate chip enable (ce) and output enable (oe ) controls. mxic's flash memories augment eprom function- ality with in-circuit electrical erasure and programming. the mx29f002t/b uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels during erase and programming, while maintaining maximum eprom features ? 262,144x 8 only ? fast access time: 70/90/120ns ? low power consumption C 30ma maximum active current C1 m a typical standby current ? programming and erasing voltage 5v 10% ? command register architecture C byte programming (7 m s typical) C block erase (16k-byte x1, 8k-byte x 2, 32k-byte x1, and 64k-byte x 3) ? auto erase (chip & block) and auto program C automatically erase any combination of sectors or the whole chip with erase suspend capability. C automatically programs and verifies data at specified address ? erase suspend/erase resume C suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation. ? status reply 1 C data polling & toggle bit for detection of program and erase cycle completion. ? sector protection C hardware method to disable any combination of sectors from program or erase operations C sector protect/unprotect for 5v only system or 5v/ 12v system ? 100,000 minimum erase/program cycles ? latch-up protected to 100ma from -1 to vcc+1v ? boot code sector architecture C t = top boot sector C b = bottom boot sector ? hardware reset pin C resets internal state machine to read mode ? low vcc write inhibit is equal to or less than 3.2v ? package type: C 32-pin pdip C 32-pin plcc C 32-pin tsop (type 1) p/n: pm0547 rev. 0.7, sep 14, 1998 2m-bit[256k x 8] cmos flash memory 2m-bit[256k x 8] cmos flash memory new advanced information compatibility. mxic's flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx29f002t/b uses a 5.0v 10% vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. mx29f002/ mx29f002n mx29f002/ mx29f002n
2 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n pin configurations 32 pdip block structure 32 plcc 32 tsop (type 1) (normal type) symbol pin name a0~a17 address input q0~q7 data input/output ce chip enable input we write enable input reset hardware reset pin/sector protect unlock oe output enable input vcc power supply pin (+5v) gnd ground pin pin description: 16 k-byte 8 k-byte 8 k-byte 32 k-byte 00000h 3ffffh (boot sector) 64 k-byte 64 k-byte 64 k-byte 3bfffh 39fffh 37fffh 2ffffh 1ffffh 0ffffh a17~a0 mx29f002t sector architecture mx29f002b sector architecture 16 k-byte 8 k-byte 8 k-byte 32 k-byte 00000h (boot sector) 64 k-byte 64 k-byte 64 k-byte 3ffffh 2ffffh 1ffffh 07fffh 05fffh 03fffh 0ffffh a17~a0 mx29f002t/b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 reset a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we a17 a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 nc on mx29f002nt/b 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 vss q3 q4 q5 q6 a12 a15 a16 reset vcc we a17 mx29f002t/b nc on mx29f002nt/b a11 a9 a8 a13 a14 a17 we vcc reset a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29f002t/b (nc on mx29f002nt/b)
3 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n block diagram control input logic program/erase high voltage write state machine (wsm) state register mx29f002 flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a17 ce oe we reset
4 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n automatic programming the mx29f002t/b is byte programmable using the automatic programming algorithm. the automatic programming algorithm does not require the system to time out or verify the data programmed. the typical chip programming time of the mx29f002t/b at room temperature is less than 2 seconds. automatic chip erase typical erasure at room temperature is accomplished in less than two second. the device is erased using the automatic erase algorithm. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are internally controlled by the device. automatic block erase the mx29f002t/b is block(s) erasable using mxic's auto block erase algorithm. block erase modes allow blocks of the array to be erased in one erase cycle. the automatic block erase algorithm automatically programs the specified block(s) prior to electrical erase. the timing and verification of electrical erase are internally controlled by the device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write a program set-up commands include 2 unlock arite cycle and a0h and a program command (program data and address). the device automatically times the programming pulse width, verifies the program, and counts the number of sequences. a status bit similar to data polling and a status bit toggling between consecutive read cycles, provides feedback to the user as to the status of the programming operation. mxic's automatic erase algorithm requires the user to write commands to the command register using stand- ard microprocessor write timings. the device will automatically pre-program and verify the entire array. then the device automatically times the erase pulse width, verifies the erase, and counts the number of sequences. a status bit similar to data polling and status bit toggling between consecutive read cycles provides feedback to the user as to the status of the programming operation. commands are written to the command register using standard microprocessor write timings. register con- tents serve as inputs to an internal state-machine which controls the erase and programming circuitry. during write cycles, the command register internally latches address and data needed for the programming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we . mxic's flash technology combines years of eprom experience to produce the highest levels of quality, relia- bility, and cost effectiveness. the mx29f002t/b electri- cally erases all bits simultaneously using fowler-nord- heim tunneling. the bytes are programmed one byte at a time using the eprom programming mechanism of hot electron injection. during a program cycle, the state-machine will control the program sequences and command register will not re- spond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has com- pleted its task, it will allow the command register to respond to its full command set. automatic erase algorithm
5 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset/read 1 xxxh f0h reset/read 4 555h aah 2aah 55h 555h f0h ra rd read silicon id 4 555h aah 2aah 55h 555h 90h adi ddi sector protect 4 555h aah 2aah 55h 555h 90h sa 00h verification x02 01h porgram 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h unlock for sector 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 20h protect/unprotect table1. software command definitions command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 1 defines the valid register com- mand sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device(when applicable). note: 1. adi = address of device identifier; a1=0,a0 =0 for manufacture code,a1=0, a0 =1 for device code (refer to table 3). ddi = data of device identifier : c2h for manufacture code, 00b0h/0034h for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2.pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address to the sector to be erased. 3.the system should generate the following address patterns: 555h or 2aah to address a0~a10. address bit a11~a17=x=don't care for all address commands except for program address (pa) and sector address (sa). write sequence may be initiated with a11~a17 in either state. 4.for sector protect verification operation : if read out data is 01h, it means the sector has been protected. if read out data is 00h, it means the sector is still not being protected.
6 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n pins ce oe we a0 a1 a6 a9 q0~q7 mode read silicon id l l h l l x v id (2) c2h manfacturer code(1) read silicon id l l h h l x v id (2) b0h/34h device code(1) read l l h a0 a1 a6 a9 d out standby h x x x x x x high z output disable l h h x x x x high z write l h l a0 a1 a6 a9 d in (3) sector protect with 12v l v id (2) l x x l v id (2) x system(6) chip unprotect with 12v l v id (2) l x x h v id (2) x system(6) verify sector protect l l h x h x v id (2) code(5) with 12v system sector protect without 12v l h l x x l h x system (6) chip unprotect without 12v l h l x x h h x system (6) verify sector protect/unprotect l l h x h x h code(5) without 12v system (7) reset x x x x x x x high z table 2. mx29f002t/b bus operation notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 1. 2. vid is the silicon-id-read high voltage, 11.5v to 12.5v. 3. refer to table 1 for valid data-in during a write operation. 4. x can be vil or vih. 5. code=00h means unprotected. code=01h means protected. a17~a13=sector address for sector protect. 6. refer to sector protect/unprotect algorithm and waveform. must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12v system" command. 7. the "verify sector protect/unprotect without 12v sysytem" is only following "sector protect/unprotect without 12v system" command.
7 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data. the device remains enabled for reads until the command register contents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid command must then be written to place the device in the desired state. silicon-id-read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufacturer and device codes must be accessible while the device resides in the target system. prom programmers typically access signature codes by rais- ing a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design practice. the mx29f002t/b contains a silicon-id-read opera- tion to supplement traditional prom programming methodology. the operation is initiated by writing the read silicon id command sequence into the command register. following the command write, a read cycle with a1=vil, a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of b0h for mx29f002t, 34h for mx29f002b. pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code(hex)code manufacture code vil vil 1 1 0 0 0 0 1 0 c2h device code vih vil 1 0 1 1 0 0 0 0 b0h for mx29f002t device code vih vil 0 0 1 1 0 1 0 0 34h for mx29f002b sector protection x vih 0 0 0 0 0 0 0 1 01h (protected) verification x vih 0 0 0 0 0 0 0 0 00h (unprotected) table 3. expanded silicon id code set-up automatic chip/block erase commands chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the automatic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. the erase and verify operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array(no erase verify command is required). if the erase operation was unsuccessful, the data on q5 is "1"(see table 4), indicating the erase operation exceed internal timing limit. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode.
8 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n set-up automatic block erase com- mands the automatic block erase does not require the device to be entirely pre-programmed prior to executing the automatic set-up block erase command and automatic block erase command. upon executing the automatic block erase command, the device will automatically program and verify the block(s) memory for an all-zero data pattern. the systemdoes not require to provide any control or timing during these operations. when the block(s) is automatically verified to contain an all-zero pattern, a self-timed block erase and verification begin. the erase and verification operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system does not required to provide any control or timing during these operations. when using the automatic block erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verify command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up command-80h. two more "unlock" write cycles are then followed by the sector erase command-30h. the sector address is latched on the falling edge of we, while the command(data) is latched on the rising edge of we. block addresses selected are loaded into internal register on the sixth falling edge of we. each successive block load cycle started by the falling edge of we must begin within 30 m s from the rising edge of the preceding we. oth- erwise, the loading period ends and internal auto block erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than block erase (30h) or erase suspend (boh) during the time- out period resets the device to read mode. erase suspend this command is only valid while the state machine is executing automatic block erase operation, and therefore will only be responded during automatic/ block erase operation. writing the erase suspend command during the block erase time-out immedi- ately terminates the time-out period and suspends the erase operation. after this command has been ex- ecuted, the command register will initiate erase sus- pend mode. the state machine will return to read mode automatically after suspend is ready. at this time, state machine only allows the command register to respond to the read memory array, erase resume and program commands. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspendend program operation is complete, the system can once again read array data within non-suspended blocks. table 4. write operation status mode q7 q6 q5 q3 q2 (note 1) (note 2) (note 1) standard mode auto program algorithm q7 toggle 0 n/a no toggle auto erase algorithm 0 toggle 0 1 toggle exceed time limits auto program q7 toggle 1 0 no toggle auto sector/chip erase 0 toggle 1 0 n/a erase suspend mode reading within erase suspended 1 no toggle 0 n/a toggle sector reading within non-erase data data data data data suspended sector earse-suspend-program q7 toggle 0 n/a n/a note: 1. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. q5 switches to '1' when an auto program or auto erase operation has exceeded the maximum timing limits. see "q5:exceeded timing limits " for more information.
9 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n set-up automatic program commands to initiate automatic program mode, a three-cycle command sequence is required. there are two "unlock" write cycles. these are followed by writing the automatic program command a0h. once the automatic program command is initiated, the next we pulse causes a transition to an active pro- gramming operation. addresses are latched on the falling edge, and data are internally latched on the rising edge of the we pulse. the rising edge of we also begins the programming operation. the system does not require to provide further controls or timings. the device will automatically provide an adequate internally generated program pulse and verify margin. if the program opetation was unsuccessful, the data on q5 is "1", indicating the program operation exceed internal timing limit. the automatic programming operation is completed when the data read on q6 stops toggling for two consecutive read cycles and the data on q7 and q6 are equivalent to data written to these two bits, at which time the device returns to the read mode(no program verify command is required). erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions.another erase suspend command can be written after the chip has resumed erasing. while the automatic erase algorithm is in operation, q7 will read "0" until the erase operation is competed. upon completion of the erase operation, the data on q7 will read "1". the data polling feature is valid after the rising edge of the secone we pulse of two write pulse sequences. the data polling feature is active during automatic program/erase algorithm or sector erase time-out.(see section q3 sector erase timer) q6:toggle bit i the mx29f002t/b features a "toggle bit" as a method to indicate to the host system that the auto program/erase algorithms are either in progress or completed. during an automatic program or erase algorithm operation, successive read cycles to any address cause q6 to toggle. the system may use either oe or ce to control the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, q6 toggles and returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase suspended. when the device is actively erasing (that is, the automatic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use q7(see the subsection on q7:data polling). if a program address falls within a protected sector, q6 toggles for approximately 2 m s after the program command sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algorithm is complete. the write operation status table shows the outputs for toggle bit i on q6. refer to the toggle bit algorithmg. write operation status data polling-q7 the mx29f002t/b also features data polling as a method to indicate to the host system that the automatic program or erase algorithms are either in progress or completed. while the automatic programming algorithm is in operation, an attempt to read the device will produce the complement data of the data last written to q7. upon completion of the automatic program algorithm an attempt to read the device will produce the true data last written to q7. the data polling feature is valid after the rising edge of the second we pulse of the two write pulse sequences.
10 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively eraseing (that is, the automatic erase alorithm is in process), or whether that sector is erase-suspended. toggle bit i is valid after the rising edge of the final we pulse in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 4 to compare outputs for q2 and q6. reading toggle bits q6/ q2 refer to the toggle bit algorithm for the following discussion. whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfuly completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation(top of the toggle bit algorithm flow chart). q5 exceeded timing limits q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). under these conditions q5 will produce a "1". this time-out condition which indicates that the program or erase cycle was not successfully completed. data polling and toggle bit are the only operating functions not of the device under this condition. if this time-out condition occurs during sector erase operation, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still functional and may be used for the program or erase operation. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. if this time-out condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector maynot be reused, (other sectors are still functional and can be reused). the q5 time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the automatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops toggling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used.
11 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n q3 sector erase timer after the completion of the initial sector erase command sequence th sector erase time-out will begin. q3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if q3 is low ("0"), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. data protection the mx29f002t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce or we will not initiate a write cycle. writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. logical inhibit sector protection with 12v system the mx29f002t/b features hardware sector protection. this feature will disable both program and erase operations for these sectors protected. to activate this mode, the programming equipment must force vid on address pin a9 and control pin oe, (suggest vid = 12v) a6 = vil and ce = vil.(see table 2) programming of the protection circuitry begins on the falling edge of the we pulse and is terminated on the rising edge. please refer to sector protect algorithm and waveform. to verify programming of the protection circuitry, the programming equipment must force vid on address pin a9 ( with ce and oe at vil and we at vih. when a1=1, it will produce a logical "1" code at device output q0 for a protected sector. otherwise the device will produce 00h for the unprotected sector. in this mode, the addresses,except for a1, are in "don't care" state. address locations with a1 = vil are reserved to read manufacturer and device codes.(read silicon id) it is also possible to determine if the sector is protected in the system by writing a read silicon id command. performing a read operation with a1=vih, it will produce a logical "1" at q0 for the protected sector. power supply decoupling in order to reduce power switching effect, each device should have a 0.1 m f ceramic capacitor connected between its vcc and gnd.
12 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n chip unprotect with 12v system the mx29f002t/b also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. it is recommended to protect all sectors before activating chip unprotect mode. to activate this mode, the programming equipment must force vid on control pin oe and address pin a9. the ce pins must be set at vil. pins a6 must be set to vih.(see table 2) refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. the unprotection mechanism begins on the falling edge of the we pulse and is terminated on the rising edge. it is also possible to determine if the chip is unprotected in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs(q0-q7) for an unprotected sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. sector protection without 12v system the mx29f002t/b also feature a hardware sector protection method in a system without 12v power suppply. the programming equipment do not need to supply 12 volts to protect sectors. the details are shown in sector protect algorithm and waveform. chip unprotect without 12v system the mx29f002t/b also feature a hardware chip unprotection method in a system without 12v power supply. the programming equipment do not need to supply 12 volts to unprotect all sectors. the details are shown in chip unprotect algorithm and waveform. power-up sequence the mx29f002t/b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of a two-step command sequence. vpp and vcc power up sequence is not required. absolute maximum ratings rating value ambient operating temperature 0 o c to 70 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 -0.5v to 13.5v notice: stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the de- vice. this is a stress rating only and functional operational sections of this specification is not implied. exposure to ab- solute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are sub- ject to change.
13 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n capacitance ta = 25 o c, f = 1.0 mhz symbol parameter min. typ max. unit conditions cin input capacitance 8 pf vin = 0v cout output capacitance 12 pf vout = 0v read operation dc characteristics ta = 0 o c to 70 o c, vcc = 5v 10% symbol parameter min. typ max. unit conditions ili input leakage current 1 m a vin = gnd to vcc ilo output leakage current 10 m a vout = gnd to vcc isb1 standby vcc current 1 ma ce = vih isb2 1 100 m a ce = vcc + 0.3v icc1 operating vcc current 50 ma iout = 0ma, f=1mhz icc2 70 ma iout = 0ma, f=10mhz vil input low voltage -0.3 (note 1) 0.8 v vih input high voltage 2.0 vcc + 0.3 v vol output low voltage 0.45 v iol = 2.1ma voh output high voltage 2.4 v ioh = -400 m a notes: 1. vil min. = -1.0v for pulse width 50 ns. vil min. = -2.0v for pulse width 20 ns. 2. vih max. = vcc + 1.5v for pulse width 20 ns if vih is over the specified maximum value, read operation cannot be guaranteed.
14 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n ac characteristics ta = 0 o c to 70 o c, vcc = 5v 10% 29f002t/b-70 29f002t/b-90 29f002t/b-12 symbol parameter min. max. min. max. min. max. unit conditions tacc address to output delay 70 90 120 ns ce=oe=vil tce ce to output delay 70 90 120 ns oe=vil toe oe to output delay 30 40 50 ns ce=vil tdf oe high to output float ( note1) 0 20 0 30 0 30 ns ce=vil toh address to output hold 0 0 0 ns ce=oe=vil note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: ? input pulse levels: 0.45v/2.4v ? input rise and fall times: 10ns ? output load: 1 ttl gate + 35pf (including scope and jig) ? reference levels for measuring timing: 0.8v, 2.0v read timing waveforms a0~17 ce oe tacc we vih vil vih vil vih vil vih vil voh vol high z high z data valid toe tdf tce data q0~7 toh add valid
15 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n dc characteristics ta = 0 o c to 70 o c, vcc = 5v 10% symbol parameter min. typ max. unit conditions icc1 (read) operating vcc current 30 ma iout=0ma, f=1mhz icc2 50 ma iout=0ma, f=10mhz icc3 (program) 50 ma in programming icc4 (erase) 50 ma in erase icces vcc erase suspend current 2 ma ce=vih, erase suspended command programming/data programming/erase operation notes: 1. vil min. = -0.6v for pulse width 20ns. 2. if vih is over the specified maximum value, programming operation cannot be guranteed. 3. icces is specified with the device de-selected. if the device is read during erase suspend mode, current draw is the sum of icces and icc1 or icc2. 4. all current are in rms unless otherwise noted.
16 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n ac characteristics ta = 0 o c to 70 o c, vcc = 5v 10% 29f002t/b-70 29f002t/b-90 29f002t/b-12 symbol parameter min. max. min. max. min. max. unit conditions toes oe setup time 50 50 50 ns tcwc command programming cycle 70 90 120 ns tcep we programming pulse width 35 45 50 ns tceph1 we programming pluse width high 20 20 20 ns tceph2 we programming pluse width high 20 20 20 ns tas address setup time 0 0 0 ns tah address hold time 45 45 50 ns tds data setup time 30 45 50 ns tdh data hold time 0 0 0 ns tcesc ce setup time before command write 0 0 0 ns tdf output disable time (note 1) 30 40 40 ns taetc total erase time in auto chip erase 2(typ.) 2(typ.) 2(typ.) s taetb total erase time in auto block erase 1(typ.) 1(typ.) 1(typ.) s tavt total programming time in auto verify 7 7 7 m s (byte program time) tbal block address load time 80 80 80 m s tch ce hold time 0 0 0 ns tcs ce setup to we going low 0 0 0 ns tvlht voltge transition time 4 4 4 m s toesp oe setup time to we active 4 4 4 m s twpp1 write pulse width for sector protect 10 10 10 m s twpp2 write pulse width for sector unprotect 12 12 12 ms notes: 1. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven.
17 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n switching test circuits switching test waveforms 2.0v 0.8v 2.4v 0.45v test points input 2.0v 0.8v output ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are < 20ns. device under test diodes=in3064 or equivalent cl 6.2k ohm 1.8k ohm +5v cl=100pf including jig capacitance
18 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n command write timing waveform add a0~17 ce oe we din tds tah data q0-7 tdh tcs tch tcwc tceph1 tcep toes tas vcc 5v vih vil vih vil vih vil vih vil vih vil add valid
19 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n automatic programming timing waveform one byte data is programmed. verify in fast algorithm and additional programming by external control are not required because these operations are executed auto- matically by internal control circuit. programming completion can be verified by data polling and toggle bit automatic programming timing waveform checking after automatic verification starts. device outputs data during programming and data after programming on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) tcwc tas tcep tds tdh tdf vcc 5v ce oe q0~q1 ,q4(note 1) we a11~a17 tceph1 tah add valid tcesc q7 command in add valid a0~a10 command in command in data in data command in command in command in data in data data tavt toe data polling 2aah 555h 555h command #aah command #55h command #a0h (q0~q7) notes: (1). q6:toggle bit, q5:tin=timing-limit bit, q3: time-out bit, q2:toggle bit
20 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes no toggle bit checking q6 not toggled verify byte ok yes q5 = 1 reset auto program completed auto program exceed timing limit no invalid command yes no
21 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n toggle bit algorithm notes: 1.read toggle bit q6 twice to determine whether or not it is toggle. see text. 2.recheck toggle bit q6 because it may stop toggling as q5 changes to "1". see text. start read q7~q0 read q7~q0 yes no toggle bit q6 =toggle? q5=1? yes no (note 1) read q7~q0 twice (note 1,2) toggle bit q6 =toggle? program/erase operation not complete, write reset command yes program/erase operation complete
22 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n automatic chip erase timing waveform all data in chip are erased. external erase verify is not required because data is erased automatically by internal control circuit. erasure completion can be verified by data polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic chip erase timing waveform tcwc tas tcep tds tdh tdf vcc 5v ce oe q0~q1 ,q4(note 1) we a11~a17 tceph1 tah tcesc q7 command in a0~a10 command in command in command in command in command in taetc data polling 2aah 555h 555h command #aah command #55h command #80h (q0~q7) notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2:toggle bit 555h 2aah 555h command in command in command #aah command in command in command #55h command in command in command #10h
23 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 10h address 555h write data 55h address 2aah reset auto chip erase exceed timing limit data polling q7 = 1 yes q5 = 1 auto chip erase completed no no invalid command yes
24 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n automatic block erase timing waveform block data indicated by a13 to a17 are erased. external erase verification is not required because data are erased automatically by internal control circuit. erasure comple- tion can be verified by data polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic block erase timing waveform tcwc tas tcep tds tdh tdf vcc 5v ce oe q0~q1, q4(note 1) we a13~a17 tceph1 tah tcesc q7 command in a0~a10 command in command in command in command in command in taetb data polling 2aah 555h 555h command #aah command #55h command #80h (q0~q7) notes: (1). q6:toggle bit, q5:timing-limit bit, q3:time-out bit, q2:toggle 555h 2aah command in command in command #aah command in command in command #55h command in command in command #30h block address 0 block address 1 tbal tceph2 block address n command in command in command in command #30h command in command #30h
25 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n automatic block erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 30h sector address write data 55h address 2aah reset auto block erase exceed timing limit data polling q7 = 1 q5 = 1 auto block erase completed load other sector addrss if necessary (load other sector address) yes no last block to erase time-out bit checking q3=1 ? toggle bit checking q6 toggled ? invalid command no yes yes no yes no
26 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n erase suspend/erase resume flowchart start write data b0h toggle bit checking q6 not toggled yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no
27 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n timing waveform for chip unprotection for system with 12v timing waveform for sector protection for system with 12v toe data oe we 12v 5v 12v 5v ce a9 a1 a6 toesp twpp 1 tvlht tvlht tvlht verify 01h a17-a13 sector address toe data oe we 12v 5v 12v 5v ce a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 sector address a17-a13
28 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n sector protection algorithm for system with 12v start set up sector addr (a17,a16,a15,a14,a13) plscnt=1 sector protection complete data=01h? yes oe=vid,a9=vid,ce=vil a6=vil activate we pulse time out 10us set we=vih, ce=oe=vil a9 should remain vid read from sector addr=sa, a1=1 protect another sector? remove vid from a9 write reset command device failed plscent=32? yes no no
29 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n chip unprotection algorithm for system with 12v start protect all sectors plscnt=1 chip unprotect complete data=00h? yes set oe=a9=vid ce=vil,a6=1 activate we pulse time out 12ms set oe=ce=vil a9=vid,a1=1 set up first sector addr all sectors have been verified? remove vid from a9 write reset command device failed plscent=1000? no increment plscent no read data from device yes yes no increment sector addr * it is recommended before unprotect the whole chip, all sectors should be protected in advance.
30 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n timing waveform for sector protection for system without 12v timing waveform for chip unprotection for system without 12v toe data oe we 5v ce a9 a1 a6 * see the following note! verify 01h a17-a13 sector address 5v note: must issue "unlock for sector protect/unprotect" command before sector protection for a system without 12v provided. q6 toggle bit polling don't care tcep toe data we 5v ce a9 a1 verify 00h a6 note: must issue "unlock for sector protect/unprotect" command before sector unprotection for a system without 12v provided. sector addresss a17-a13 oe tcep 5v q6 toggle bit polling don't care * see the following note!
31 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n sector protection algorithm for system without 12v start set up sector addr (a17,a16,a15,a14,a13) plscnt=1 sector protection complete data=01h? yes oe=vih,a9=vih ce=vil,a6=vil activate we pulse to start data don't care set ce=oe=vil a9=vih read from sector addr=sa, a1=1 protect another sector? write reset command device failed plscent=32? yes no increment plscnt no write "unlock for sector protect/unprotect" command(table1) toggle bit checking q6 not toggled no yes yes no
32 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n chip unprotection algorithm for system without 12v start protect all sectors plscnt=1 chip unprotect complete data=00h? yes set oe=a9=vih ce=vil,a6=1 activate we pulse to start data don't care set oe=ce=vil a9=vih,a1=1 set up first sector addr all sectors have been verified? write reset command device failed plscent=1000? no increment plscent no read data from device yes yes no increment sector addr * it is recommended before unprotect the whole chip, all sectors should be protected in advance. write "unlock for sector protect/unprotect" command (table 1) toggle bit checking q6 not toggled yes no
33 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n id code read timing waveform mode tacc tce tacc toe toh toh tdf data out c2h b0h/34h vid vih vil add a9 add a2-a8 a10-a17 ce oe we a1 data out data q0-q7 vcc 5v vih vil vih vil vih vil vih vil vih vil vih vil
34 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n ordering information plastic package part no. access time operating current standby current package (ns) max.(ma) max.( m a) mx29f002tpc-70 70 30 1 32 pin pdip mx29f002tpc-90 90 30 1 32 pin pdip mx29f002tpc-12 120 30 1 32 pin pdip mx29f002ttc-70 70 30 1 32 pin tsop (normal type) mx29f002ttc-90 90 30 1 32 pin tsop (normal type) mx29f002ttc-12 120 30 1 32 pin tsop (normal type) mx29f002tqc-70 70 30 1 32 pin plcc mx29f002tqc-90 90 30 1 32 pin plcc mx29f002tqc-12 120 30 1 32 pin plcc mx29f002bpc-70 70 30 1 32 pin pdip mx29f002bpc-90 90 30 1 32 pin pdip mx29f002bpc-12 120 30 1 32 pin pdip mx29f002btc-70 70 30 1 32 pin tsop (normal type) mx29f002btc-90 90 30 1 32 pin tsop (normal type) mx29f002btc-12 120 30 1 32 pin tsop (normal type) mx29f002bqc-70 70 30 1 32 pin plcc mx29f002bqc-90 90 30 1 32 pin plcc mx29f002bqc-12 120 30 1 32 pin plcc
35 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n ordering information plastic package part no. access time operating current standby current package (ns) max.(ma) max.( m a) MX29F002NPC-70 70 30 1 32 pin pdip mx29f002npc-90 90 30 1 32 pin pdip mx29f002npc-12 120 30 1 32 pin pdip mx29f002nttc-70 70 30 1 32 pin tsop (normal type) mx29f002nttc-90 90 30 1 32 pin tsop (normal type) mx29f002nttc-12 120 30 1 32 pin tsop (normal type) mx29f002ntqc-70 70 30 1 32 pin plcc mx29f002ntqc-90 90 30 1 32 pin plcc mx29f002ntqc-12 120 30 1 32 pin plcc mx29f002nbpc-70 70 30 1 32 pin pdip mx29f002nbpc-90 90 30 1 32 pin pdip mx29f002nbpc-12 120 30 1 32 pin pdip mx29f002nbtc-70 70 30 1 32 pin tsop (normal type) mx29f002nbtc-90 90 30 1 32 pin tsop (normal type) mx29f002nbtc-12 120 30 1 32 pin tsop (normal type) mx29f002nbqc-70 70 30 1 32 pin plcc mx29f002nbqc-90 90 30 1 32 pin plcc mx29f002nbqc-12 120 30 1 32 pin plcc note. revision history revision # description page date 0.2 device codes are revised to 00b0h/0034h compatible with amd's jun/29/98 0.3 the feature of sector unprotect is revised to chip unprotect jul/07/98 0.4 device id codes are revised to b0h/34h compatible with amd's jul/29/98 0.5 sector protect verification is added on the software command table aug/18/98 0.6 modify the block diagram aug/28/98 0.7 modify the q3 status into "0" for exceeded time limits in write p8 sep/10/98 operation status table
36 rev. 0.7, sep 14, 1998 p/n: pm0547 mx29f002/ mx29f002n mx29f002/ mx29f002n package information 32-pin plastic dip item millimeters inches a 42.13 max. 1.660 max. b 1.90 [ref] .075 [ref] c 2.54 [tp] .100 [tp] d .46 [typ.] .050 [typ.] e 38.07 1.500 f 1.27 [typ.] .050 [typ.] g 3.30 .25 .130 .010 h .51 [ref] .020 [ref] i 3.94 .25 1.55 .010 j 5.33 max. .210 max. k 15.22 .25 .600 .101 l 13.97 .25 .550 .010 m .25 [typ.] .010 [typ.] note: each lead certerline is located within .25mm[.01 inch] of its true position [tp] at a maximum at maximum material condition. a 17 32 16 1 f d e c b h ij g m 0~15 k l 32-pin plastic leaded chip carrier (plcc) item millimeters inches a 12.44 .13 .490 .005 b 11.50 .13 .453 .005 c 14.04 .13 .553 .005 d 14.98 .13 .590 .005 e 1.93 .076 f 3.30 .25 .130 .010 g 2.03 .13 .080 .005 h .51 .13 .020 .005 i 1.27 [typ.] .050 [typ.] j .71 [ref] .028 [ref] k .46 [ref] .018 [ref] l 10.40/12.94 .410/.510 (w) (l) (w) (l) m .89r .035r n .25[typ.] .010[typ.] note: each lead certerline is located within .25mm[.01 inch] of its true position [tp] at a maximum at maximum material condition. 1 b a 4 5 9 13 14 17 20 21 25 29 32 cd e f g h i k j l m n 30
32-pin plastic tsop item millimeters inches a 20.0 .20 .078 .006 b 18.40 .10 .724 .004 c 8.20 max. .323 max. d 0.15 [typ.] .006 [typ.] e .80 [typ.] .031 [typ.] f .20 .10 .008 .004 g .30 .10 .012 .004 h .50 [typ.] .020 [typ.] i .45 max. .018 max. j 0 ~ .20 0 ~ .008 k 1.00 .10 .039 .004 l 1.27 max. .050 max. m .50 .020 n0 ~5 .500 note: each lead certerline is located within .25mm[.01 inch] of its true position [tp] at a maximum at maximum material condition. a b c d e f g h i j kl m n macronix international co., ltd headquarters : tel : +886-3-578-8888 fax : +886-3-578-8887 europe office : tel : +32-2-456-8020 fax : +32-2-456-8021 japan office : tel : +81-44-246-9100 fax : +81-44-246-9105 singapore office : tel : +65-747-2309 fax : +65-748-4090 taipei office : tel : +886-2-2509-3300 fax : +886-2-2509-2200 macronix america inc. tel : +1-408-453-8088 fax : +1-408-453-8488 chicago office : tel : +1-847-963-1900 fax : +1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. 37 mx29f002/ mx29f002n mx29f002/ mx29f002n

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